The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for patterning a semiconductor device having a magnetic tunneling junction (MTJ) structure.
Recently, researches have been conducted with respect to next-generation memory devices that can replace dynamic random access memory (DRAM) and flash memory device. For example, one of next-generation memory devices is spin transfer torque random access memory (STT-RAM). The STT-RAM stores different data, which is bit data ‘0’ or ‘1,’ based on whether the magnetic tunneling junction structure is magnetized or not. More specifically, the magnetic tunneling junction structure is formed of a sandwich structure including two ferromagnetic layers and an insulation layer. Generally, the insulation layer may be embodied as Al2O3. The insulation layer functions as a tunneling barrier disposed between the two ferromagnetic layers.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device having a magnetic tunneling junction structure.
As shown in FIG. 1A, a lower electrode conductive layer 11 is formed over a substrate 10 with a predetermined lower structure formed therein.
A first ferromagnetic layer 12 is formed over the lower electrode conductive layer 11. An insulation layer 13 as a tunneling barrier is formed over the first ferromagnetic layer 12. A second ferromagnetic layer 14 is formed over the insulation layer 13. Thus, a magnetic tunneling junction structure is formed over the lower electrode conductive layer 11.
An upper electrode conductive layer 15 is formed over the second ferromagnetic layer 14. The upper electrode conductive layer 15 is used as a hard mask for subsequent patterning of the lower layers, i.e., the second ferromagnetic layer 14, the insulation layer 13, the first ferromagnetic layer 12 and the lower electrode conductive layer 11.
A photoresist pattern 17 is formed over the upper electrode conductive layer 15 to pattern the upper electrode conductive layer 15, the second ferromagnetic layer 14, the insulation layer 13, the first ferromagnetic layer 12 and the lower electrode conductive layer 11. Herein, before forming the photoresist pattern 17, an anti-reflection layer 16 may be formed over the upper electrode conductive layer 15 to prevent reflection during a lithography process.
As shown in FIG. 1B, an upper electrode 15A is formed by etching the upper electrode conductive layer 15 using the photoresist pattern 17 as an etch barrier. In this etching process, the photoresist pattern 17 may be damaged.
The second ferromagnetic layer 14, the insulation layer 13, the first ferromagnetic layer 12 and the lower electrode conductive layer 11 are sequentially etched using at least the upper electrode 15A as an etch barrier, to form a second ferromagnetic pattern 14A, an insulation pattern 13A, a first ferromagnetic pattern 12A and a lower electrode 11A, respectively. Thus, a magnetic tunneling junction structure 100 including the first ferromagnetic pattern 12A, the insulation pattern 13A and the second ferromagnetic pattern 14A sequentially disposed between the lower electrode 11A and the upper electrode 15A is formed.
Since the size of a memory device having the magnetic tunneling junction is comparatively small, a lithography equipment such as ArF is required to form the photoresist pattern 17. Also, the height of the photoresist pattern 17 is restricted to be within low limits. Thus, the upper electrode 15A may be damaged due to margin deficiency of the photoresist pattern 17, and the second ferromagnetic pattern 14A under the upper electrode 15A may be damaged.